This relates to methods of fabricating semiconductor devices with field effect transistors having gates that straddle fins of channel forming material (so-called FinFETs).
Conventional integrated circuit devices, such as SRAM devices, have NMOS and PMOS fin field effect transistors (FinFETs) with different channel crystal orientations laid out in a non-aligned fin layout (referred to as a “non-Manhattan” layout). Adjacent fins of different conductivity type are rotated by 45° to accommodate for the different crystal orientations of the substrate surfaces.
FIG. 1 (Prior Art) illustrates a conventional layout for a multiple gate FinFET (MuGFET) device 100. As shown, MuGFET 100 has a semiconductor material fin 130 straddled by a saddle-like gate 120. The fin 110 and gate 120 are formed on an oxide layer 140 (e.g., SiO2) formed on a semiconductor substrate. The channels for MuGFET 100 are located on the sidewalls 150 of the fin 130. For a usual <110> notch (001) surface wafer, the sidewall 150 of the fin 130 has a (110) crystal orientation if fin 130 is laid out at 0° or 90° rotation with respect to the notch. If the rotation of the fin 130 is laid out at 45° with respect to the notch, the fin 130 sidewalls 150 will have a (100) crystal orientation.
A (110) crystal orientation surface is good for channel hole mobility but poor for channel electron mobility, while the (100) crystal orientation channel surface is poor for channel hole mobility but good for channel electron mobility. Thus, a (110) sidewall orientation is a preferred orientation for PMOS MuGFETs and a (100) sidewall orientation is a preferred orientation for NMOS MuGFETs. To provide preferred surface orientations for PMOS and NMOS MuGFETs on the same substrate, conventional fabrication methods use mixed rotations of the fins 130 of 0° (or 90°) and 45°. Such mixed rotations require increases in layout area of an integrated circuit device by approximately 25% and increase lithography difficulties.
FIG. 2A (Prior Art) illustrates a top view of an example non-Manhattan layout design of a conventional SRAM storage cell which uses both PMOS and NMOS FinFETs. As shown, SRAM storage cell 200 has a plurality of fins 210 with runs of 0° and 45° rotations straddled by gates 220. Fins 210 have enlarged pad portions away from the gates 220 which provide locations for connection to source/drain regions by contacts 215. Gates 220 have enlarged pad portions away from the fins 210 for connection to gate electrodes by contacts 225. Using industry standards for spacing between components and measurements taken between centers of outside contact points of contacts 215, 225, the example conventional layout for SRAM storage cell 200 shown in FIG. 2 occupies a layout area of approximately 500 nm by approximately 812.5 nm, or approximately 406,250 nm2. (Elements of the layout for storage cell 200 given in FIG. 2A are marked to show correspondence with source/drains S, D or S/D and gates G of pull-up transistors PT1, PT2, drive transistors DT1, DT2 and access transistors AT1, AT2 of a typical storage cell schematic diagram such as given in FIG. 1b of U.S. Pat. No. 7,087,493 which is reproduced as FIG. 2B herein.)